This invention relates generally to Field Effect Transistor (FET) and Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices, and more particularly to FinFET devices having channels comprising fins formed above a supporting substrate and extending between horizontally disposed source and drain regions which are also formed above the supporting substrate.
As has been the trend in the past, continued improvement in the performance of FET devices can be achieved by “scaling” those devices to smaller sizes to increase device speed.
Whereas the conventional FET device had a single gate electrode, recently double gate structures have been developed which form a gate on both sides of the body or channel of the FET. The double gate structure permits better current and short channel control in a device with smaller space requirements on the surface of a semiconductor.
FinFET devices are double gate FET devices with a vertical fin which forms the channel of the FET and with double gates formed on either side of the fin which may be separate or which may be interconnected to function as a single gate electrode.
U.S. Pat. No. 6,611,029 of Ahmed et al entitled “Double Gate Semiconductor Device Having Separate Gates” describes a FinFET device with two separate, independent gate electrodes formed on opposite sides of the fin. The device comprises a Silicon-On-Insulator (SOI) FET device. In SOI devices a layer of silicon overlies a substrate composed of an insulator such as silicon dioxide.
U.S. Pat. No. 6,413,802 of Hu et al for “FinFET Transistor Structures Having a Double Gate Channel Extending Vertically From a Substrate and Methods of Manufacture” describes a single or multiple fin FinFET device formed over an insulative layer. A vertical channel fin which is formed over the insulative layer is covered by a gate oxide layer. A double gate electrode extends across the channel fin. The device is formed by etching away portions of the silicon layer of a SOI structure to form the source drain islands and the vertical fin which connects the source/drain islands together. The double gate provides enhanced drive current and effectively suppresses short channel effects. A plurality of parallel fins is shown connecting between the source and the drain for increased current capacity, with a double gate structure straddling all of the parallel channel fins.
The Hu et al. patent described the FinFET art in the following paragraphs. Huang et al. “Sub-50 nm FinFET PMOS” IEDM Tech. Dig., pp. 75–78 (1999), Huang et al. “Sub-50 nm P-Channel FinFET” IEEE Transactions on Electron Devices, VOL. 48, No. 5, pp. 880–886 (May 2001) describe FinFET devices. Wong et al. “Self-Aligned (Top and Bottom) Double Gate MOSFET with a 25 nm Thick Silicon Channel”, IEDM 97-427-430, 16.6.1–16.6.4 (1997 IEEE) describes a double gate MOSFET with the gate electrode formed above and below a thin silicon channel.
Leobandung et al. “Wire-channel and wrap-around gate metal-oxide-semiconductor field-effect transistors with a significant reduction of short channel effects” J. Vac. Sci. Technol. B 15(6), pp. 2791–2794 (November/December 1997) describes a MOSFET with a wire channel patterned by Electron Beam Lithography (EBL) suspended between the source and the drain before formation of the gate electrode. Then an 11 nm thick gate oxide is formed followed by formation of a gate electrode deposited by LPCVD. Then the gate was patterned by a second EBL step followed by a Reactive Ion Etching (RIE) step.
U.S. Pat. No. 6,610,576 of Nowak entitled “Method for Forming Asymmetric Dual Gate Transistor” describes asymmetric doping of dual gates which are asymmetric in size.
U.S. Pat. No. 6,583,469 of Fried et al. entitled “Self-Aligned Dog-Bone Structure for FinFET Applications and Methods to Fabricate the Same” describes a structure with a FinFET channel and source/drain regions which are tapered in width to reduce gate to source/drain capacitance.
U.S. Pat. No. 6,475,869 of Yu entitled “Method of Forming a Double Gate Transistor Having an Epitaxial Silicon/Germanium Channel Region” describes a FinFET device with a vertical channel fin composed of silicon lined on sidewalls with SiGe formed on a BOX layer. The channel fin is capped by layer of silicon nitride. The gate electrode surrounding three sides of the channel fin.
U.S. Pat. No. 6,635,909 of Clark et al. entitled “Strained Fin FETs Structure and Method” describes a Fin FET structure in which a vertical fin formed on an insulator with a central portion composed of SiGe and Si and end portions composed of Si whereby the SiGe produces strain within the central portion creates strain to enhance carrier mobility.